The invention lies in the field of semiconductor manufacture and pertains, more specifically, to a semiconductor structure in an integrated circuit having an insulating layer on a support and having an interconnect arranged above the insulating layer. The invention also pertains to a method for fabricating the structure.
In integrated circuits, for the purpose of driving the individual components, interconnects are required as wiring. In many cases, these interconnects also lead over an active region or other conductive structures, giving rise to parasitic capacitances which impair the speed of the circuit.
It is a fundamental goal in integrated circuits to reduce these parasitic capacitances. This is especially true as the integration level increases, since the interconnects increasingly have to be routed over active regions and the use of thicker insulation layers below the interconnects has led to an increase in the aspect ratios and topology steps that occur, which in turn leads to difficulties in terms of process engineering.
Furthermore, interconnects in integrated circuits are used as word lines of transistors. Over an active region in the semiconductor substrate which has two spaced-apart regions, doped oppositely to the conductivity type of the substrate, an interconnect forms the gate of a MOS transistor. The transistor can be switched by means of the gate potential. In many cases it is desirable for a transistor in a circuit to be always open (or always closed) independently of the gate potential. A predetermined integrated circuit can be programmed in this way.
It is accordingly an object of the invention to provide a semiconductor structure having an interconnect, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which, on the one hand, has a low parasitic capacitance, and also a method for fabricating such a semiconductor structure. It is a further object to specify a semiconductor structure having an interconnect which allows simple programming of transistors, and also a corresponding programming method.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor structure in an integrated circuit, comprising:
an insulating layer on a support;
an interconnect above the insulating layer and separated by a cavity from the insulating layer;
an insulating covering laterally adjoining, in the form of a spacer, the interconnect, the cavity and an upper surface of the interconnect;
the covering having an opening formed therein, extending beyond the interconnect on one side of the interconnect; and
a further insulation layer covering the covering and the opening.
The invention is based on the idea of arranging the interconnect (i.e., the conductor track) on a cavity. The lower surface of the cavity adjoins an insulating layer on a support, the upper surface of the cavity adjoins the interconnect and, on two opposite sides, said cavity adjoins an insulating covering. The insulating covering also covers the side walls of the interconnect. In other words, below a section of the electrically conductive interconnect there extends a cavity having essentially the same lateral dimensions as the interconnect. The cavity is preferably filled with air or an essentially inert gas; in particular, it is partially evacuated.
Transversely with respect to the interconnect direction, the cavity essentially has the same width as the interconnect width. In the direction of the interconnect, the cavity can extend below the entire interconnect. However, the interconnect can also have a section in which it is arranged on a lower conductive layer; in other words, the cavity is virtually filled here with the lower conductive layer, in particular with n-doped or pxe2x88x92 doped polysilicon. In such a section, the interconnect can be used as the gate of a transistor. The interconnect is preferably composed of a metal silicide.
The support over which the interconnect with underlying cavity is arranged may contain an active region in the form of two spaced-apart doped SID regions of a MOS transistor. In this case, then, the semiconductor structure constitutes a MOS transistor in which the interconnect forms the gate and is isolated from the gate oxide by a cavity. Such a transistor is always in the open state or in the closed state (normally on or normally off depending on the threshold voltage chosen) independently of the gate potential.
With the above and other objects in view there is also provided, in accordance with the invention, a method of fabricating a semiconductor structure, which comprises:
forming an insulating layer on a support;
applying a lower conductive layer and an upper conductive layer on the insulating layer and patterning the conductive layers in track form;
forming an insulating covering in the form of a spacer on side walls of the lower and upper conductive layers;
producing an opening in the insulating covering, the opening extending beyond the upper conductive layer only on one side of the upper conductive layer and uncovering a surface of the lower conductive layer;
selectively removing the lower conductive layer; and
closing the opening with a further insulating material.
In accordance with a preferred embodiment, the lower conductive layer is fabricated from doped polysilicon and the upper conductive layer is fabricated from a silicide.
In other words, the method for fabricating the semiconductor structure provides for an insulating layer to be applied on a support and then for a lower conductive layer and an upper conductive layer to be applied. The upper conductive layer may also be a multiple layer. The two conductive layers are patterned, preferably simultaneously, in track form in accordance with the interconnect to be fabricated. An insulating covering is formed on the uncovered surfaces of the lower and upper conductive layers. An opening is then produced in the insulating covering, which at least partly uncovers a surface of the lower conductive layer. Through this opening, the lower conductive layer is selectively removed with the aid of an essentially isotropic etching method. The opening is closed with a further insulating material. Preferably, the lower conductive layer is composed of n-doped or p-type polysilicon, and the upper conductive layer is composed of a silicide. KOH, in particular, can be used for etching the lower conductive layer, i.e. for producing the cavity.
If the cavity is intended to be produced over a relatively long section of the interconnect, it is advantageous to arrange a plurality of openings in the covering at a predetermined distance from one another along the interconnect.
With the aid of the method, a transistor formed in the semiconductor substrate can be programmed in a simple manner: depending on the arrangement of an opening in the insulating covering and on the etching time, either a cavity is formed above the channel region of the transistor, or the lower conductive layer remains and forms part of the gate. Only in the latter case is the transistor controlled by way of the potential of the gate. The invention thus enables a mask-programmable circuit.
It is a significant advantage that it is possible to use customary method steps for fabricating an interconnect, in particular a word line in a memory circuit, and it is necessary merely to carry out an etching process (using phototechnology) for opening the insulating covering and the subsequent cavity etching process. In some DRAM concepts, it is even the case that these etching processes are already implemented for forming other structuresxe2x80x94for example a conductive strap which connects the selection transistor to a storage capacitorxe2x80x94, and so all that is required is design optimization for the opening of the insulating covering. An example of such a fabrication method is disclosed in U.S. Pat. No. 5,185,294 (European EP 543 158 A2) and U.S. Pat. No. 5,731,218 (European EP 651 433 A1xe2x80x94in particular columns 5 and 6).
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor structure having an interconnect, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.